What is Makefile in Linux? How does it work?

Run and compile your programs more efficiently with this handy tool
Makefile is used for automatic compilation and linking. A project consists of many files. Any change to a file will result in the relinking of the project. However, not all files need to be recompiled. Makefile can record file information and decide which files need to be recompiled when linking!

The make tool is usually used when you need to run or update a task after some source files have changed. The make tool needs to read a Makefile (or makefile) file, which defines a series of tasks to be performed. You can use make to compile source code into an executable program. Most open source projects use make to compile the final binary files, and then use the make install command to perform the installation.
This article will show how to use make and Makefile through some basic and advanced examples. Before you begin, make sure you have make installed on your system.

The basic example still starts with printing "Hello World". First, create a directory named myproject and create a Makefile file in the directory with the following content:

say_hello:
echo "Hello World"

Execute make in the myproject directory, and the following output will appear:

$ make
echo "Hello World"
Hello World

In the above example, "say_hello" is similar to function names in other programming languages. This is called a target. Following the target are the prerequisites or dependencies. For simplicity, we did not define preconditions in this example. The echo 'Hello World' command is called a recipe. These steps are based on the pre-conditions to achieve the goal. The goal, preconditions, and steps together make up a rule.

To summarize, the syntax of a typical rule is:

Objective: Prerequisites
<TAB> Steps

As an example, a target can be a binary file based on a precondition (source code). On the other hand, a precondition can also be a target that depends on other preconditions.

final_target: sub_target final_target.c
Recipe_to_create_final_target
sub_target: sub_target.c
Recipe_to_create_sub_target

The target does not need to be a file, it can also be just the name of a step, as in our example. We call this a "pseudo target"

Going back to the example above, when make is executed, the entire command echo "Hello World" is displayed, followed by the actual execution result. If you do not want the command itself to be printed, you need to add @ before echo.

say_hello:
@echo "Hello World"

Re-run make and you will see the following output:

$ make
Hello World

Next, add the following pseudo targets to the Makefile: generate and clean:

say_hello:
@echo "Hello World"
generate:
@echo "Creating empty text files..."
touch file-{1..10}.txt
clean:
@echo "Cleaning up..."
rm *.txt

When we run make later, only the say_hello target is executed. This is because the first target in a Makefile is the default target. Normally the default target is called, which is what you see as the first target in most projects: all. all is responsible for calling its target. We can override the default behavior by using the special pseudo goal .DEFAULT_GOAL .

Add .DEFAULT_GOAL to the beginning of the Makefile:

.DEFAULT_GOAL := generate

Make will use generate as the default target:

$ make
Creating empty text files...
touch file-{1..10}.txt

As the name implies, the .DEFAULT_GOAL pseudo-target can only define one goal. This is why many Makefiles include the target all, which can call multiple targets.
Next, delete .DEFAULT_GOAL and add the all goal:

all: say_hello generate
say_hello:
@echo "Hello World"
generate:
@echo "Creating empty text files..."
touch file-{1..10}.txt
clean:
@echo "Cleaning up..."
rm *.txt

Before running, let's add some special pseudo targets. .PHONY is used to define targets that are not files. By default, make will call the steps under these pseudo targets without checking the existence of the file name or the last modification date. The complete Makefile is as follows:

.PHONY: all say_hello generate clean
all: say_hello generate
say_hello:
@echo "Hello World"
generate:
@echo "Creating empty text files..."
touch file-{1..10}.txt
clean:
@echo "Cleaning up..."
rm *.txt

The make command calls say_hello and generate:

$ make
Hello World
Creating empty text files...
touch file-{1..10}.txt

clean should not be put into all, or into the first target. clean should be called manually when cleaning is needed, the calling method is make clean

$ make clean
Cleaning up...
rm *.txt

Now that you have a basic understanding of Makefile, let's look at some advanced examples.

Advanced Examples Variables In the previous examples, most of the targets and preconditions were fixed, but in real projects, they are usually replaced by variables and patterns.

The simplest way to define a variable is to use the = operator. For example, to assign the command gcc to the variable CC:

CC = gcc

This is called recursive variable expansion, and is used in rules like this:

hello: hello.c
${CC} hello.c -o hello

As you might expect, these steps will expand to:

gcc hello.c -o hello

Both ${CC} and $(CC) can refer to gcc. But if a variable tries to assign itself to itself, it will cause an infinite loop. Let's verify this:

CC = gcc
CC = ${CC}
all:
@echo ${CC}

Running make at this point will result in:

$ make
Makefile:8: *** Recursive variable 'CC' references itself (eventually). Stop.

To avoid this, you can use the := operator (this is called simple variable expansion). The following code will not cause the above problem:

CC := gcc
CC := ${CC}
all:
@echo ${CC}

Modes and Functions The following Makefile uses variables, modes, and functions to compile all C code. Let's analyze it line by line:

# Usage:
# make # compile all binary
# make clean # remove ALL binaries and objects
.PHONY = all clean
CC = gcc # compiler to use
LINKERFLAG = -lm
SRCS := $(wildcard *.c)
BINS := $(SRCS:%.c=%)
all: ${BINS}
%: %.o
@echo "Checking.."
${CC} ${LINKERFLAG} $< -o $@
%.o: %.c
@echo "Creating object.."
${CC} -c $<
clean:
@echo "Cleaning up..."
rm -rvf *.o ${BINS}

Lines starting with # are comments
The line .PHONY = all clean defines two pseudo targets, all and clean.
The variable LINKERFLAG defines the parameters that the gcc command needs to use in the step.
SRCS := $(wildcard *.c): $(wildcard pattern) is a function related to the file name. In this example, all files with the ".c" suffix will be stored in the SRCS variable.
BINS := $(SRCS:%.c=%): This is called a substitution reference. In this example, if the value of SRCS is 'foo.c bar.c', then the value of BINS is 'foo bar'.
The line all: ${BINS}: The pseudo-target all invokes all values ​​in the ${BINS} variable as sub-targets.
rule:

%: %.o
@echo "Checking.."
${CC} ${LINKERFLAG} $< -o $@

Let's use an example to understand this rule. Assume that foo is a value in the variable ${BINS}. % will match foo (% matches any target). Here is what the rules look like after they are expanded:

foo: foo.o
@echo "Checking.."
gcc -lm foo.o -o foo

As shown above, % is replaced by foo. $< is replaced by foo.o. $< is used to match the preset condition, $@ matches the target. This rule will be called once for each value in ${BINS}.
rule:

%.o: %.c
@echo "Creating object.."
${CC} -c $<

Each precondition in the previous rule will be treated as a target in this rule. Here is what it looks like after it’s expanded:

foo.o: foo.c
@echo "Creating object.."
gcc -c foo.c

Finally, in the clean target, all binaries and compiled files are removed.
Here is the rewritten Makefile, which should be placed in a directory with a foo.c file:

# Usage:
# make # compile all binary
# make clean # remove ALL binaries and objects
.PHONY = all clean
CC = gcc # compiler to use
LINKERFLAG = -lm
SRCS := foo.c
BINS := foo
all: foo
foo: foo.o
@echo "Checking.."
gcc -lm foo.o -o foo
foo.o: foo.c
@echo "Creating object.."
gcc -c foo.c
clean:
@echo "Cleaning up..."
rm -rvf foo.o foo

These together form a makefile. Of course, these functions are too few, and many other projects can be added. But the purpose is: let the compiler know which other files it needs to depend on to compile a file. When those dependent files are changed, the compiler will automatically find that the final generated file is out of date and recompile the corresponding module.

Summarize

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