Introduction to network drivers for Linux devices

Wired network: Ethernet Wireless network: 4G, wifi, Bluetooth, 5G

Summary: Internal MAC + external PHY + RJ45 socket (built-in network transformer) constitute a complete embedded network interface hardware.

The internal MAC peripheral will connect to the external PHY chip through the MII or RMII interface. The MII/RMII interface is used to transmit network data. In addition, the master needs to configure or read the PHY chip, that is, read and write the internal registers of the PHY, so a control interface called MIDO is also required. MDIO is very similar to IIC, and also has two wires, a data line called MDIO, and a clock line called MDC.

(1) Data link layer MAC is the abbreviation of Media Access Control, which is the media access control sublayer protocol. This protocol is located in the lower half of the data link layer in the OSI seven-layer protocol, and is mainly responsible for controlling the physical medium that connects the physical layer. When sending data, the MAC protocol can determine in advance whether the data can be sent. If it can be sent, some control information will be added to the data, and finally the data and control information will be sent to the physical layer in the specified format. When receiving data, the MAC protocol first determines the input information and whether a transmission error occurs. If there is no error, the control information will be removed and sent to the LLC layer. The Ethernet MAC is defined by the IEEE-802.3 Ethernet standard.

(2) Physical layer PHY is the physical interface transceiver, which implements the physical layer. It includes MII/GMII (media independent interface) sublayer, PCS (physical coding sublayer), PMA (physical medium attachment) sublayer, PMD (physical medium dependent) sublayer, and MDI sublayer.

(3) MII stands for Media Independent Interface. “Media independent” means that any type of PHY device can work normally without redesigning or replacing the MAC hardware. Includes two independent channels for transmitter and receiver respectively. Each channel has its own data, clock, and control signals. The MII data interface requires a total of 16 signals, including TX_ER, TXD<3:0>, TX_EN, TX_CLK, COL, RXD, RX_EX, RX_CLK, CRS, RX_DV, etc.

(4) RMII stands for Reduced Media Independent Interface, which is a simplified version of the MII interface. The RMII interface only requires 7 data lines, which is 9 less than MII, greatly facilitating board wiring. A bus clock of 50 MHz is generally required. Like MII, RMII supports 10M and 100M bus interface speeds .

(5) GMII is the MII interface of Gigabit Ethernet . It also has a corresponding RGMII interface, which means a simplified GMII interface. GMII uses 8-bit interface data and a working clock of 125MHz , so the transmission rate can reach 1000Mbps. It is also compatible with the 10/100 Mbps operating mode specified by MII.

(6) MDIO interface
MDIO stands for Management Data Input/Output, which literally means management data input and output interface. It is a simple two-wire serial interface, one MDIO data line and one MDC clock line. The driver can access any register of the PHY chip through the two lines MDIO and MDC. The MDIO interface supports up to 32 PHYs. Only one PHY can be operated at the same time, so how to distinguish these 32 PHY chips? Just like IIC, use the device address. The device addresses of all PHY chips under the same MDIO interface cannot conflict and must be unique. For specific device address values, refer to the corresponding PHY data manual.

Therefore, the MAC and external PHY chip are connected mainly through the MII/RMII and MDIO interfaces, and other pins such as reset and interrupt may also be required.

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